1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor memory device and, more particularly, to a method for fabricating a capacitor of a semiconductor memory device.
2. Description of the Related Art
A high capacitance capacitor is more advantageous for the purpose of securing reliability of a semiconductor device. Especially for memory device among the semiconductor elements, a capacitor is required whose capacitance is as high as possible so as to preserve refresh due to automatic extinction of a data value. Accordingly, every effort has been made to increase capacitance in the memory products.
Capacitance may be increased by enlarging a surface area of a storage electrode or by using a dielectric film whose dielectric constant is great. However, most dielectric films are still developing except for an NO film and an ONO film. Accordingly, capacitance is generally increased by enlarging a surface area of the storage electrode.
A surface area of a storage electrode may be enlarged with a stack type, a cylinder type, a fin type, or a trench type. The trench type and the stack type are mainly used. For the trench type, a capacitor is made by depositing a storage electrode layer after digging a trench on a semiconductor substrate. The trench type may enlarge the surface area of a capacitor, but have a complex and difficult isolation or processing procedure.
On the contrary, the stack type has a simple processing procedure. Furthermore, it is not complex to increase the height of the stack for the purpose of increasing capacitance. However, this increased height makes lithography difficult during a subsequent metal wiring process. That is, a step between a cell and a peripheral region becomes so great that a focus margin of lithography is reduced, thereby making the metal wiring thin or generating a cut-off or bridge. In view of solving the foregoing matters, it is required that a storage electrode have a small step between a cell and a peripheral region. Since a dielectric film having very high dielectric constant is not generally available yet, an HSG (hemispherical grain) method is generally used to enlarge a surface area of a capacitor.
FIG. 1A to FIG. 1C illustrate sequential processes of a method for fabricating a capacitor of a prior semiconductor memory device.
Referring to FIG. 1A, a device isolation layer 11 for defining an active region and an inactive region is formed on a semiconductor substrate 10. A gate electrode layer 13 is formed on a gate oxide layer over the semiconductor substrate 10. An oxide layer 14, which is formed from a lower oxide layer 14a and an upper oxide layer 14b and serves as an insulating layer, is formed on the semiconductor substrate 10, including the gate electrode layer 13, where a transistor is formed.
A bit line 15 is formed in the oxide layer 14, between the lower oxide layer 14a and the upper oxide layer 14b. The oxide layer 14 is etched to form a contact hole 16 by using a contact hole formation mask until a surface of the semiconductor substrate 10 is exposed. The contact hole 16 is filled with a conductive material such as a polysilicon, thereby forming a plug 17 which is electrically connected to the semiconductor substrate 10.
Referring to FIG. 1B, a polysilicon layer 18 serving as a conductive layer is formed on the oxide layer 14 including the plug 17. The polysilicon layer 18 is etched by using the storage electrode formation mask, thereby forming a storage electrode 18 which is electrically connected to the plug 17. An HSG layer 19 enlarging a surface area of a capacitor is formed on a surface of the storage electrode 18.
Referring to FIG. 1C, a capacitor dielectric film 20 is formed on the oxide layer 14 including the HSG layer 19. A polysilicon layer 21, which is doped to serve as an upper capacitor electrode, is deposited on the capacitor dielectric film 20 to form a capacitor.
As mentioned above, a stack type capacitor has merits in that the processing procedure is simple and a throughput is good. However, it is difficult for the stack type capacitor to have enough capacitance value by scaling-down the device design rule according to the high density of a device and form a pattern whose size may prevent a bridge with an adjacent capacitor during formation of an HSG layer.
The reason is as follows. A space between patterned storage electrodes should be wide enough so as to grow an HSG layer. Accordingly, a delicate lithography process is needed and the height of an electrode should be increased so as to atone for a surface area, which may greatly influence the subsequent metal wiring process. As the HSG layer is grown on a surface of a patterned storage electrode, as shown in symbol `A` of FIG. 1B, a part of the HSG layer is connected between the storage electrodes, thereby generating a minute micro-bridge. Since the micro-bridge results in device failure, reliability may be degraded.